Agilent Technologies 35670A Service Manual download pdf (Page 48)

48 Agilent 35670A Supplement

4 Service Guide

Power Supply Voltage Distribution

In the table the references to paths to the A8 and A9 boards is

deleted since the circuits are now on the A17 CPU board.

A8 Memory

The memory is in now incorporated into the A17 CPU board

and the following information should be transferred to the A17

signal descriptions:

Everything else in the section should be disregarded.

Page in original guide 9-6

Page in original guide 9-8 through 9-11

BD16-31 Buffered Data Bus–This is the buffered processor data bus from the A17 CPU assembly. This

bus is further buffered on the A17 CPU assembly to create the Device Data bus.

DSACK0n—

DSACK1n

Data Strobe Acknowledge–During a write cycle, DSACK signals are set low when the device

being addressed is ready to end the memory access cycle. When DSACK0n goes low and

DSACK1n is low, 32 bits of data are valid. When DSACK0n goes low and DSACK1n is high, 8

bits of data are valid.

PA0—PA26 Processor Address Bus–This is the processor address bus from the CPU. PA0 and PA1 also

operate with SIZE0 and SIZE1 to specify the alignment of the operand.

PASn Processor Address Strobe–A low on this line starts a memory access cycle. This line pulses

low when a valid address is on the processor address bus.

PD0—15 Processor Data Bus–This is the processor data bus.

PRW Processor Read/Write–This line is high when the current memory cycle is a read, and low

when the current memory cycle is a write.

SCL Serial Clock–This is the serial clock for the IIC bus. The IIC controller on the CPU assembly

generates this clock to synchronize the transfer of data on the IIC bus.

SDA Serial Data–This is the IIC bus bidirectional data line.

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Agilent Technologies 35670A Service Manual Page 48