Agilent Technologies 4294A Specifications download pdf (Page 91)

As a result of extremely high integration of logic LSIs using MOS FETs, the thickness of the MOS

FETs’ gate oxide is becoming thinner (less than 2.0 nm), and such MOS FETs have been produced

recently. In evaluating these kinds of MOS FETs, leakage current becomes larger by the tunneling

effect because the capacitance value of a thin gate oxide has high impedance, and most of the test

signal flows as leakage current. Consequently, measurement of the thin gate oxide cannot be per-

formed accurately. To solve this problem, test frequency should be set higher (1 MHz or more) than

usual to reduce the impedance value of the thin gate oxide as low as possible. It is also important to

simplify the measurement configuration to reduce residuals that exist in the measurement path. If

you perform high-frequency C-V measurement using the 4TP configuration, the measurement error

increases due to the residual inductance of the guard cable that is connected between the probe

heads. Also, the compensation does not work well because the distance between probes easily

varies. To solve this problem, a simplified 2T configuration with the 42941A impedance probe, as

shown in Figure 5-27, is highly recommended for accurate high-frequency C-V measurement.

Figure 5-27. Example of high-frequency C-V measurement system configuration

Coaxial cable

Probe head

Wafer prober

Chuck

Agilent 4294A

42941A Impedance Probe

5-17

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 125 126

No comments

Agilent Technologies 4294A Specifications Page 91